The present invention relates to a semiconductor device having a capacitor and a method for manufacturing the same, and more particularly to a semiconductor device having a capacitor of large capacitance and a method for manufacturing the same.
One type of memory device formed on the semiconductor substrate is the dynamic RAM (hereinafter referred to as DRAM) composed of a MOS transistor and a MOS capacitor. In the above DRAM, data is stored according to whether or not the MOS capacitor is charged. Also, data is read out by discharging the MOS capacitor to a bit line through the MOS transistor and then detecting the change in its potential.
Recently, miniaturization and large-scaled integration of DRAMs have advanced in accordance with the progress of semiconductor technology. A major problem in the large scaled integration of DRAM is how to increase cell capacitance while reducing memory cell size.
It is known that the capacitance of a capacitor is directly proportional to the dielectric constant and the surface area of the dielectric film, and inversely proportional to the thickness of the dielectric film. Therefore, in order to increase the capacitance, it is necessary to use an insulation layer with a larger dielectric constant, enlarge the surface area of the dielectric film, or make the dielectric film thinner. However, it is undesirable to reduce the thickness of the dielectric film to increase the capacitance, because this decreases the reliability of the semiconductor device. Additionally, it has been suggested to use as a dielectric film an insulating layer with large dielectic constant such as a Ta.sub.2 O.sub.5 film, but this is not yet practically in use. Accordingly, it is desirable to enlarge the effective surface area of the capacitor in order to increase its capacitance. A great deal of research has been carried out and various methods for increasing the effective area of a capacitor have been suggested, for example, a capacitor having a trench structure obtained by forming its storage electrode on an etched trench in the semiconductor substrate.
Recently, a method for producing a larger capacitance in a semiconductor memory device without enlarging the area of the cell nor heightening the storage electrode was suggested and is drawing great attention. That is, the technology for forming a polycrystalline silicon layer with an uneven surface as a storage electrode having an enlarged surface area due to this unevenness is disclosed in the 1990 Extended Abstracts of the 22nd Conference on Solid State Device and Materials, pp. 869 to 872 (Yoshio Hayashide et al.) and pp. 873 to 876 (H. Watanabe et al.).
FIG. 1 illustrates a sectional view of a stacked capacitor having uneven surface of the electrode described in the above papers. According to the method of Watanabe et al., after growing a field oxide 2 on a silicon substrate 1 by an LOCOS method, a first impurity-doped polycrystalline silicon layer as a gate electrode 3 is formed and then a source region 4 and a drain region 5 are formed by ion implantion. Then, an oxide layer 6 as an insulation layer is formed. Thereafter, to form a storage electrode 7 as the capacitor's first electrode, polycrystalline silicon is deposited by an LPCVD method at 550.degree. C. to form a first polycrystalline film. The specific temperature, 550.degree. C., corresponds to the transition temperature of the film structure, from amorphos to polycrystalline. The surface area of a polycrystalline silicon film deposited at this is about twice as large as that deposited at different temperatures.
Thereafter, a photoresist (not shown in FIG. 1) is coated on the first polycrystalline silicon film and is exposed and developed using a mask, thereby forming a photoresist pattern. Subsequently, storage electrode 7 is formed by ething the first polycrystalline silicone film using the photoresist pattern as an etching mask and then removing the photoresist pattern. Thereafter, a dielectric film 8 composed of oxide/nitride is formed on the thus-obtained storage electrode 7. A second electrode 9 as a plate electrode of the capacitor is formed by depositing polycrystalline silicon on dielectric film 8 to form a second polycrystalline silicon film.
According to the above method, twice the capacitance can be obtained by applying the above-mentioned polycrystalline silicon film to the storage electrode for a stacked capacitor.
Also, Hayashide et al. teach that a capacitor attains 1.5 times as much capacitance as one with a conventional polycrystalline silicon electrode, when the storage electrode is formed by depositing polycrystalline silicon at 575.degree. C.
However, when manufacturing a capacitor by this method, critical temperature adjustment is necessary when depositing the polycrystalline silicon. Also, the thickness of the polycrystalline silicon film as the storage electrode of the capacitor is an important factor in controlling the surface unevenness. Therefore, it is difficult to obtain various capacitor structures. Moreover, since after the depositing process, the uneven surface of the sidewall thereof is removed since the deposited polycrystalline silicon film is patterned by photolithography and an etching process, thereby reducing the effect of the enlargement of the capacitor's effective surface area. To overcome these problems, the present inventors have conducted many experiments, as a result, have accomplished the present invention.